1. Field of the Invention
The present invention relates to a flash memory device, and specifically, to a flash memory device improving loading speed and reducing current consumption, by selecting input data through IO pad and enabling a data load path for data to be programmed while disabling the data load path for data to be erased.
2. Discussion of Related Art
In applying data to NAND type flash memory cells, a data loading command is applied to the flash memory device and data are loaded on a page buffer 40 by way of IO pads with increasing address values in sequence. The data to be programmed, generally, are transmitted to the page buffer in the unit of byte or word in sequence. If data to be programmed, corresponding to a data volume of one page, are all loaded on the page buffer, the data stored in the page buffer are programmed in a memory cell array by a page program command all at once.
The page buffer conserves the potential of power supply voltage level Vcc as its initial value. That is, the initial value of the page buffer is set by a program bias condition. Typically, data input through IO pads are continuously written in the page buffer by way of data paths in a power supply voltage level Vcc or a ground voltage level Vss.
In a normal case of a NAND type flash memory device, the data should be loaded by 512×8 bit in 512 cycle times. But if the logical polarity of data is opposite to the previous data while loading the data, it increases current consumption, which causes power consumption heavier especially when 8-bit data is transferred at the same time.